The present invention relates to a reference voltage generating circuit, and, more particularly, to a technique effectively applied to a reference voltage generating circuit built into a semiconductor integrated circuit device that permits operation down to such low voltages as battery voltages.
A reference voltage generating circuit such as shown in FIG. 8 using MOSFETs (insulated-gate field-effect transistors) is available. This circuit includes n-channel MOSFETs Q3, Q4, Q5 with low threshold voltages and a MOSFET Q6 with a standard threshold voltage and derives the difference between the threshold voltages of MOSFETs Q5 and Q6 as a reference voltage Vr. For temperature compensation, p-channel MOSFETs Q1 and Q2 form a current mirror circuit, whose current ratio is set at an appropriate value. Another example of such a reference voltage generating circuit is found in the Japanese Patent Laid-Open No. 249212/1987.